The assignee of the present application has developed RapidChip™ technology that lets designers quickly and affordably create high-performance, complex, customized ICs. RapidChip is a chip building technique, which dramatically lowers cost, risk and time-to-market. Each RapidChip™ slice is a pre-manufactured, pre-verified chip at the density and power of an ASIC in which all silicon-based layers and some metal layers have been built, leaving the top metal layers to be completed with the customer's unique intellectual property. The customer selects a desired slice that best accommodates their application, and then creates a proprietary design using the final metal layers of the chip.
The fundamental technology used in the RapidChip technology is the metal customization of a partially manufactured semiconductor device, e.g., an ASIC, in which all silicon layers of a slice have been fabricated. Rapidchip customization layers are limited to VIA1 (that layer which provides connection between metal 1 and metal 2) and above, which include metal layers M2-M8, the lowest programmable level being layer VIA1. Each slice incorporates diffused memory blocks, PLLs, IP blocks from a CoreWare® library, configurable transistor fabric, and an I/O ring made up of configurable and dedicated I/Os for specific requirements. For example, most slices made are fabricated with several instances of medium density static RAM (SRAM), but it has been observed that a ROM is utilized in less than 10% of all custom RapidChip designs. This makes it inefficient for a chip manufacturer to employ an actual ROM solution in a platform ASIC, such as RapidChip. However, the chip manufacturer must still offer a ROM solution to satisfy the demands of certain customers, even if only for that 10%.
Accordingly, there is a need for a more efficient method for providing memory on a platform ASIC that will accommodate custom designs that require RAM and/or ROM. The present invention address, such a need.